In the computing industry, unsustainable power and thermal overheads have saturated achievable clock frequencies in modern processors, limiting the ability to rely on instruction-level parallelism and higher clock frequencies to achieve performance growth. The continuing quest for higher performance has started a trend focusing on thread- and task-level parallelism, leading to the emergence of homogeneous and heterogeneous multi-/many-core computing.
Heterogeneous computing focuses on the deployment of multiple types of processing elements within a single workflow, and allowing each processing element to perform the operations to which it is best suited within a given application. A processing element could be a general-purpose processor (GPP), a special-purpose processor (i.e. digital signal processor (DSP) or graphics processing unit (GPU)), a co-processor, or custom acceleration logic (application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA)), for example.
One area of interest within the heterogeneous computing community is the use of reconfigurable logic processing elements such as FPGAs as a co-processor or accelerator to a conventional host processor such as a GPP. By implementing kernels within an application that are responsible for the majority of the run-time directly in FPGA hardware, the performance of the entire application may be significantly increased. One barrier to the use of FPGAs to boost performance, however, is the requirement for hardware design, a task ill-equipped for software engineers who often lack hardware knowledge.
One prior art approach to simplify the design process and raise design abstraction from hardware description language is the use of Matlab-to RTL and Simulink-to-RTL Flows. When simple graphical designs are mapped to FPGA protopying or evaluation boards which are fully integrated in the flow, the designers do not need FPGA knowledge. Examples include the integration of Xilink ML-boards in Xilink System Generator tool. A disadvantage of this flow however is that designers do need FPGA knowledge when targeting non-integrated FPGA platforms, or when complex designs are being developed. These two situations are typically encountered in real-world projects. Additionally, implemented designs are not portable to other platforms.
An alternative prior art approach is to employ C-to-RTL flows to compile high-level programming languages such as C into register transfer level (RTL) description, followed by FPGA synthesis. This prior art approach suffers from the need for time-consuming FPGA synthesis. Further, the resulting implementations are typically not portable because of necessary integration work.
Accordingly, there is a need for an environment for the development of an application, executable in a reconfigurable logic based heterogeneous computing system that supports an all-software development flow, design portability and eliminates traditional time-consuming synthesis.